| As the DDR Design Verification Engineer, you will participate in the definition and development of the verification methodology. You will be responsible for developing test plans, test-benches (drivers, monitors and checkers/scoreboard etc..) and test cases. You will be executing test plans to verify the MLSoC functionality, performance and coverage analysis. You will work closely with the Architecture, RTL/uArch, and cross-functional teams.
Required Background:
- Experience with block level, cluster level or chip/SoC level verification.
- Proficiency in system verilog, UVM, constrained random and coverage driven verification methodology.
- Experience with development of test bench components, test plans for DDR/LPDDR IP verification.
- Good system verilog programming, debug and problem solving skills.
- Scripting languages, python or perl is a plus.
Preferred Qualifications:
- DDR controller and/or DDR-IO verification experience.
- BS in Computer Science/EE with 8+ years of experience or MS in computer science/EE with 6+ years of experience in SoC design verification. |
