| Your responsibilities will include RTL coding, design and reviews, synthesis, static timing analysis, and coverage analysis. This means working very closely with the architecture team, verification team, and back-end team as well as cross-functional teams. The primary design target is an SoC ASIC, with machine learning being a key component.
Role and Responsibilities:
- Design methodology, micro-architecture, RTL.
- Static timing analysis, verification/emulation support, back-end support, chip bringup.
- Work with the architecture team to develop the uArch and subsequently write the RTL.
- Develop the design methodology, starting with the machine learning architecture (MLA).
- Synthesis, static timing analysis, equivalence checking.
- Work with the back-end team on floorplanning and other PD-related activities.
- Work with the verification and emulation teams.
- Help with chip validation, bringup, and characterization.
Minimum Requirements:
- Masters degree in electrical engineering, computer engineering, or a related field.
- 10+ years professional experience as a hardware design engineer, SOC design engineer, hardware engineer, or related position.
- Experience must include SOC design methodology, micro-architecture, emulation and back-end development, and chip bringup.
- Experience must include developing ARM CPU based SoCs, Network-on-Chip and interfaces such as MIPI-CSI, Ethernet and PCIe. |
