|As the Machine Learning Design Verification Engineer, you will participate in definition and develop the verification methodology. You will be responsible for developing test plans, test-benches (drivers, monitors and checkers/scoreboard etc.) and test cases. You will be executing test plans to verify the functionality, performance and coverage analysis. You will work closely with the architecture, RTL/uArch, and cross-functional teams.
- Experience with block level, cluster level or chip/SoC-level verification.
- Proficiency in system verilog, UVM, constrained random and coverage driven verification methodology.
- Experience with development of test bench components, test plans for IP verification.
- Good system verilog programming, debug and problem solving skills.
- Scripting languages, python or perl is a plus.
- BS in Computer Science/EE with 8+ years of experience or MS in Computer Science/EE with 6+ years of experience in SoC design verification.
Desired Qualifications and Skills:
- Machine Learning (ML) and/or CPU verification experience.