|- Mixed signal circuit design at the cell, block, and possibly system level for Marvells next generation IP designs in advanced CMOS finfet technology nodes.
- Design focus on DDR/LPDDR PHY interface which includes but not limited to DLLs, Phase interpolators, CDRs, clocking, voltage regulation, reference generation, and equalization.
- Capable of PHY / IO feature definition and architectural planning.
- Drive a design from planning, implementation, and carry it through layout and post-layout analysis.
- In-depth knowledge on high speed DDR, LPDDR or HBM standard.
- Strong understanding of mixed-signal fundamentals.
- Good written and verbal communication skills.
- Ability to independently conduct analysis and provide solutions on complex design issues which may involve timing, layout, SI, PI...etc.
- Expertise with standard EDA tools (Hspice, Cadence).
- Experience with completing designs through chip tape out in nanometer technology nodes.
- Experience working in finfet technology nodes is preferred.
- Experience with RTL / Verilog coding is preferred.
- Experience with system level SI and PI analysis a plus.
- Experience with MATLAB and PERL a plus.
- Experience with timing analysis tools, such as Primetime or Nanotime, a plus.
- Must have effective interpersonal and teamwork skills, potentially at a leadership position if needed.
- Demonstrates good analysis and problem-solving skills.
- Inherent sense of urgency and accountability.
- Must have the ability to multi-task in a fast-paced environment.
- BSEE with 10-15 years, MSEE or PhD with 5-10 years of experience.