|- Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers.
- Write a verification test plan using random techniques and coverage analysis, and work with designers to ensure it is complete.
- Develop tests and tune the environment to achieve coverage goals.
- Debug failures and work with designers to resolve issues.
- Verify boot code
- Architecting, developing, and maintaining tools to streamline the design of state-of-the-art multicore SoCs.
- Transform the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment.
- Unit and regression testing of software tools.
- Turn verification tests into hardware-test patterns.
- BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience.
- Extremely strong programming skills including object-oriented design and implementation. Proficient using C++, Verilog, and ARM assembly
- Experience with System Verilog preferably UVM.
- Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.
- Experience with scripting language such as Python or Perl and EDA Verification tools.
- Good understanding of Linux OS.
- Understanding of networking protocols a plus.
- Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.
- Requires the ability to accept and work with differing opinions
- cannot be a close-minded developer.
- Must be able to learn on the fly and work in a fast-paced environment.