|- Verify functionality of high-performance SOC.
- Architect and implement simulation test bench in UVM.
- Develop and execute test-plans for verifying correctness and performance of the design.
- Own and debug failures in simulation to root-cause problems.
- Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations
- Coach and mentor junior engineers of the team when necessary to achieve successful project outcomes.
- BS Computer Engineering, Electrical Engineering, or Computer Science with 10-15+ years of design verification experience OR Masters degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
Requirements and Skills:
- Strong background in SoC verification methodology and test bench development using HVL such as Verilog, System Verilog, UVM
- Strong verification skills, understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations).
- C/C++ programming skills
- Prior experience in functional verification of Ethernet network system is preferred.
- Knowledge of unix/linux environment and scripting (shell/Perl/Python) is a plus.
- Must have effective interpersonal and teamwork skills. Excellent communication skills.
- Ability to interface internally and externally with all levels of the organization.
- Participate in problem solving and quality improvement activities.
- Demonstrates good analysis and problem-solving skills. Inherent sense of urgency and accountability. Demonstrate initiative and a bias for thoughtful action.
- Grounded, detail-oriented, always backs up ideas with facts. Must have the ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various data-sets.
- Must have the ability to multi-task in a fast-paced environment.